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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Table 6. Transmit Interface Timing (Continued)
Bridge Core User’s Guide
Symbol
tS terr
tH terr
tS tsx
tH tsx
tS tadr
tH tadr
tP dtpa
tP stpa
tP ptpa
Description
TERR Set-up time to TFCLK
TERR Hold time to TFCLK
TSX Set-up time to TFCLK
TSX Hold time to TFCLK
TADR[4:0] Set-up time to TFCLK
TADR[4:0] Hold time to TFCLK
TFCLK High to DTPA Valid
TFCLK High to STPA Valid
TFCLK High to PTPA Valid
Min.
2
0.5
2
0.5
2
0.5
1.5
1.5
1.5
Max.
—
—
—
—
—
—
6
6
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 5. Transmit Physical Timing
TFCLK
TENB
TDAT[31:0]
TPRTY
TSOP
TEOP
TMOD[1:0]
TERR
TSX
tStenb
tStdat
tStprty
tStsop
tSteop
tStmod
tSterr
tStsx
tStadr
tHtenb
tHtdat
tHtprty
tHtsop
tHteop
tHtmod
tHterr
tHtsx
tHtadr
TADR[]
tPdtpa
DTPA[]
tPstpa
STPA
tPptpa
PTPA
Notes on Transmit Interface I/O Timing:
1. When a set-up time is speci?ed between an input and a clock, the set-up time is the time in nanoseconds from
the 1.4V point of the input to the 1.4V point of the clock.
2. When a hold time is speci?ed between an input and a clock, the hold time is the time in nanoseconds from the
1.4V point of the clock to the 1.4V point of the input.
3. Output propagation delay time is the time in nanoseconds from the 1.4V point of the reference signal to the
1.4V point of the output.
4. Maximum output propagation delays are measured with a 30pF load on the outputs.
14
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